One Hot State Assignment Verilog Define

Some of the advantages of onehot encoding in FSMs are as follows:

  1. Low switching activity. Since only single bit is switched at a time, the power consumption is less and it is less prone to glitches.
  2. Simplified encoding. One can determine the state just by looking at the bit position of '1' in the current state variable.

The disadvantage of this technique is that it requires more number of flops. So, if one has a FSM with 10 different states, one needs 10 flops, while one needs only 4 flops when using decimal encoding.

Coming to your question, it is simple to change to onehot encoded FSM. One needs to implement a statement based on the position of in the variable. The code snippet can be implemented as follows:

A simple example is available at this link and explanation is over here. Cummings paper is also a good source for more info.

EDIT: As @Greg pointed out, it was a copy-paste error. A combinational block must use blocking assignments.

1. How do you convert a XOR gate into a buffer and a inverter (Use only one XOR gate for each)?
Answer



2. Implement an 2-input AND gate using a 2x1 mux.
Answer



3. What is a multiplexer?
Answer

A multiplexer is a combinational circuit which selects one of many input signals and directs to the only output.

4. What is a ring counter?
Answer

A ring counter is a type of counter composed of a circular shift register. The output of the last shift register is fed to the input of the first register. For example, in a 4-register counter, with initial register values of 1100, the repeating pattern is: 1100, 0110, 0011, 1001, 1100, so on.

5. Compare and Contrast Synchronous and Asynchronous reset.
Answer

Synchronous reset logic will synthesize to smaller flip-flops, particularly if the reset is gated with the logic generating the d-input. But in such a case, the combinational logic gate count grows, so the overall gate count savings may not be that significant. The clock works as a filter for small reset gl…

0 thoughts on “One Hot State Assignment Verilog Define

Leave a Reply

Your email address will not be published. Required fields are marked *